From: Subject: Syntaxe VHDL Date: Tue, 3 Mar 2009 22:57:17 +0100 MIME-Version: 1.0 Content-Type: multipart/related; type="text/html"; boundary="----=_NextPart_000_0000_01C99C53.669577E0" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 This is a multi-part message in MIME format. ------=_NextPart_000_0000_01C99C53.669577E0 Content-Type: text/html; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Content-Location: http://amouf.chez.com/syntaxe.htm Syntaxe VHDL

=20








=

A

ABS, AFTER, AND, ARCHITECTURE,= ASSERT, ATTRIBUTS.

Abs

Voir les op=E9rateurs.

After

AFTER sp=E9cifie un temps de r=E9ponse d'un signal par = rapport =E0 son=20 =E9v=E9nement.
Deux modes de d=E9lai sont possibles INERTIAL = (d=E9faut) ou TRANSPORT.=20 Le mode INERTIAL ne propage pas les impulsions plus courtes que le temps = de=20 propagation.

Syntaxe

Exemple

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY nor2 IS
      PORT (a,b : IN std_logic;
      z : OUT std_logic);
    END=20 nor2;

    ARCHITECTURE behavior OF nor2 IS
    BEGIN
      dly0: PROCESS(a,b)
      BEGIN
        z <=3D a NOR b AFTER 10 ns; -- temps de propagation est de=20 10ns
      END PROCESS dly0;
    END = behavior;
And

Voir les op=E9rateurs.

Architecture

D=E9clare une architecture comportementale ou = structurelle d'une=20 entit=E9. Ceci permet de d=E9finir les relations entre les = entr=E9es/sorties d'une=20 fonction.=20

Syntaxe

Exemple

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY fulladd = IS
      PORT (x,y,cin : IN bit;
      sum, cout : OUT bit);
    END=20 fulladd;

    ARCHITECTURE behavior OF fulladd IS
    BEGIN
      sum <=3D x XOR y XOR cin;
      cout <=3D (x AND y) OR (x AND = cin) OR (y=20 AND cin);
    END behavior;

Assert

ASSERT est une instruction de d=E9boggage.
Test si = une=20 condition est TRUE. Dans le cas contraire, reporte un message sur = l'=E9cran du=20 simulateur.
ASSERT est tr=E8s utile pour v=E9rifier les violations de = timing.
L'option de SEVERITE permet de d=E9finir le niveau = d'importance de=20 l'alerte. Voici la liste des niveaux :
NOTE, WARNING, ERROR, FAILURE. = Le=20 dernier niveau arr=EAte normalement la simulation.

    Guide des niveaux de s=E9v=E9rit=E9 :
      Note : utilis=E9 pour information seulement
        "Note : Chargement de donn=E9es d'un fichier"
      Warning : = utilis=E9=20 pour fournir une information sur une erreur en instance
        "Warning : D=E9tection d'un pic"
      Error : utilis=E9 pour = information=20 seulement
        "Error : Violation du temps d'initialisation"
      Failure : = raporte=20 une grosse erreur
        "Failure : Ligne RESET instable"

Syntaxe

    ASSERT condition
      [REPORT string] [SEVERITY severity_level];

Exemple

    check_setup: PROCESS (clk, d)
    BEGIN
      IF (clk'EVENT AND clk=3D'1') THEN -- test si front montant de = clk
        ASSERT d'STABLE(setup_time) -- regarde si d est stable pendant=20 setup_time
          REPORT "Setup Violation..." -- affiche un message = d'avertissement si=20 pas de stabilit=E9
          SEVERITY WARNING;
      END = IF;
    END PROCESS=20 check_setup;

Attributs

Les attributs permettent d'ajouter des informations=20 suppl=E9mentaires =E0 un signal, variable ou un composant.

Syntaxe

    object_name'attribut_name

Syntaxe des = attributs pour=20 le type ARRAY ou scalaire
    X'HIGH =E9l=E9ment le plus grand ou borne maximale
    X'LOW = =E9l=E9ment le plus=20 petit ou borne minimale
    X'LEFT =E9l=E9ment de gauche ou borne de=20 gauche
    X'RIGHT =E9l=E9ment de droite ou borne de=20 droite
Syntaxe des attributs pour les objets = d=E9clar=E9s dans un=20 ARRAY ou un SUBTYPE
    x'RANGE =E9l=E9ment range de x
    x'REVERSE_RANGE =E9l=E9ment range = de x dans=20 l'ordre inverse
    x'LENGTH x'HIGH - x'LOW + 1=20 (integer)
Syntaxe des attributs pour = SIGNAL
    x'EVENT retourne TRUE si x change d'=E9tat
    x'ACTIVE retourne TRUE = si x a=20 chang=E9 durant le dernier interval
    x'LAST_EVENT retourne une = valeur=20 temporelle depuis le dernier changement de x
    x'LAST_ACTIVE retourne = une=20 valeur temporelle depuis la derni=E8re transition de x
    x'LAST_VALUE = retourne=20 la derni=E8re valeur de x
Ces attributs cr=E9ent un = nouveau=20 SIGNAL
    x'DELAYED(t) cr=E9e un signal du type de x retard=E9 par = t
    x'STABLE(t)=20 retourne TRUE si x n'est pas modifi=E9 pendant le temps = t
    x'QUIET(t) cr=E9e un=20 signal logique =E0 TRUE si x n'est pas modifi=E9 pendant un temps=20 t
    x'TRANSACTION cr=E9e un signal logique qui bascule lorsque x est = change=20 d'=E9tat
Exemple
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY d_flop = IS
      PORT (d,clk,clr, set : IN std_logic;
            q : OUT std_logic);
    END = d_flop;

    ARCHITECTURE=20 behavior OF d_flop IS -- fonctionnement d'une bascule D
    CONSTANT = clrit:=20 std_logic :=3D '0';
    CONSTANT setit: std_logic :=3D = '1';
    BEGIN
      PROCESS (clk, clr, set) -- liste de sensibilit=E9
      BEGIN
        IF (clk=3D'1') AND (clk'EVENT) THEN -- TRUE sur un front montant = de=20 clk
          IF (clr =3D '0') THEN -- si clr est =E0 0
            q <=3D clrit; -- clr actif, q =E0 0
          ELSIF (set = =3D '0') THEN --=20 si set est =E0 0
            q <=3D setit; -- set actif, q =E0 1
          ELSE
            q <=3D d; -- si ni clr ni set, alors q =3D d
          END=20 IF;
        END IF;
      END PROCESS;
    END=20 behavior;






B







C

CASE, CASSE, COMMENTAIRE, = COMPONENT, CONFIGURATION, CONSTANT. =

Case

On utilise CASE pour permettre le choix entre = plusieurs actions.=20 Cette instruction est tr=E8s utile dans les machines d'=E9tats.
En = fin de liste,=20 on peut ajouter WHEN OTHERS qui permet de donner une action =E0 tous les = choix qui=20 n'ont pu =EAtre trouv=E9s dans la liste.

Syntaxe

Exemple

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY handshk = IS
      PORT (clk,req : IN std_logic;
          ack : OUT std_logic);
    END = handshk;

    ARCHITECTURE=20 behavior OF handshk IS
    CONSTANT st0 : std_logic_vector(0 TO 1) :=3D = "00";
    CONSTANT st1 : std_logic_vector(0 TO 1) :=3D = "01";
    CONSTANT st2 :=20 std_logic_vector(0 TO 1) :=3D "10";
    CONSTANT st3 : = std_logic_vector(0 TO 1)=20 :=3D "11";
    SIGNAL state : std_logic_vector(0 TO 1) :=3D = "00";
    BEGIN
      checkreq: PROCESS
      BEGIN
        WAIT UNTIL clk =3D '1'; -- attend un front montant de = clk
        CASE state=20 IS -- state est la variable du choix
          WHEN st0 =3D> -- si state =3D st0 soit '00'
            IF req =3D '1' THEN -- si req =3D '1'
              state <=3D st1; -- on incr=E9mente la machine = d'=E9tat
            END=20 IF;
          WHEN st1 =3D> -- si state =3D st1
            state <=3D st2; -- la machine d'=E9tat passe =E0 = st2
          WHEN st2=20 =3D>
            state <=3D st3;
          WHEN st3 =3D>
            state <=3D st0; -- la machine d'=E9tat est boucl=E9e vers = st0
          WHEN OTHERS =3D> NULL;
        END = CASE;
      END PROCESS=20 checkreq;

      ackit: PROCESS (state) -- ce PROCESS g=E8re un bit = de=20 propagation
      BEGIN
        CASE state IS
          WHEN st2 | st3 =3D> -- si state vaut st2 ou st3
            ack <=3D '1'; -- passer ack =E0 1
          WHEN OTHERS = =3D> -- dans=20 tous les autres cas de state
            ack <=3D '0'; -- laisser ack =E0 0
        END = CASE;
      END=20 PROCESS ackit;
    END behavior;

Casse

La casse n'est pas sensible. Il n'y a pas de = diff=E9renciation=20 minuscule/majuscule.

Commentaire

Un commentaire d=E9bute par deux traits (signe moins) = : --=20

Exemple
sum <=3D x XOR y; -- OU EXCLUSIF de x et y.=20

Component

COMPONENT permet d'=E9crire d'un programme sous la = forme=20 structurelle. En effet, il faut d=E9clarer et d=E9finir les composants = de la=20 fonction puis dans le corps de l'architecture, il suffit de les = connecter en=20 suivant un sch=E9ma structurel.
Cette m=E9thode d'=E9criture permet = aussi la=20 description hi=E9rarchique.
Quatre blocs sont =E0 distinguer dans une = telle=20 d=E9finition :

Syntaxe
D=E9claration
    COMPONENT COMPONENT_name
      [local_generic_clause]
      [local_port_clause]
    END = COMPONENT;

D=E9finition du brochage
    instantiation_label: COMPONENT_name
    [GENERIC MAP=20 (local_generic_list)]
    [PORT MAP local_port_list]

    Exemple

    L'exemple propose de synth=E9tiser = le sch=E9ma=20 ci-dessous :

      ENTITY fulladd IS
        PORT (x,y,cin : IN bit; sum,cout : OUT bit);
      END=20 fulladd;


      ARCHITECTURE struct OF fulladd IS -- 1=B0 = rescencement de=20 tous les composants du sch=E9ma

        COMPONENT xor2 -- d=E9claration du OU-EXCLUSIF
          PORT (a, b : IN bit;
              q: OUT bit);
        END = COMPONENT;

        COMPONENT or2 --=20 d=E9claration du OU
          PORT (a, b : IN bit;
              q: OUT bit);
        END = COMPONENT;

        COMPONENT and2 --=20 d=E9claration du ET
          PORT (a,b : IN bit;
              q: OUT bit);
        END COMPONENT;
        SIGNAL in1, = in2, in3:=20 bit;

        BEGIN -- 2=B0 affectation des liaisons du sch=E9ma aux = broches des=20 composants
        u1: xor2
          PORT MAP(x, -- affectation par nom
              y, -- on retrouve les signaux du sch=E9ma et les signaux du=20 composant
              in1);

        u2: or2
          PORT MAP(in2, -- affectation par position
              in3, -- c'est l'ordre de passage qui d=E9termine des=20 connections
              cout);

        u3: xor2
          PORT MAP(a =3D> in1,b =3D> = cin,q=3D>sum);

        u4: and2
          PORT MAP(a =3D> in1,b =3D> = cin,q=3D>in3);

        u5: and2 -- il=20 faut passer tous les composants en revue
          PORT MAP(a =3D> x,b =3D> y, q=3D>in2);
      END = struct;

      CONFIGURATION fulladd_config OF fulladd IS -- 3=B0 = attribution=20 des circuits =E0 leur ENTITY
      FOR struct
        FOR u1,u3: xor2 USE ENTITY WORK.xor2; -- u1 et u3 h=E9ritent du=20 comportement de xor2_arch d=E9fini plus loin
        END FOR;

        FOR = u2: or2=20 USE ENTITY WORK.or2; -- affectation de u2
        END FOR;

        FOR = u4,u5: and2=20 USE ENTITY WORK.and2;-- affectation de u4 et u5
        END = FOR;

      END=20 FOR;
      END fulladd_config;

      -------------------------------- = contenu=20 d'une autre biblioth=E8que

      ENTITY and2 IS
        PORT (a,b : IN bit;q : OUT bit);
      END = and2;

      ARCHITECTURE=20 behv OF and2 IS
      BEGIN
        q<=3Da and b;
      END behv;


      ENTITY or2 IS
        PORT (a,b : IN bit;q : OUT bit);
      END = or2;

      ARCHITECTURE behv=20 OF or2 IS
      BEGIN
        q<=3Da or b;
      END behv;


      ENTITY xor2 IS
        PORT (a,b : IN bit;q : OUT bit);
      END = xor2;

      ARCHITECTURE=20 behv OF xor2 IS
      BEGIN
        q<=3D((not a) and b) or (a and (not b));
      END behv;
      Configuration

      CONFIGURATION s'utilise en combinaison avec COMPONENT.=20

      Syntaxe

        CONFIGURATION configuration_name OF entity_name IS
            FOR architecture_name
              {use_clause}
              {component_configuration}
            END = FOR;
        END=20 [configuration_name];

      Constantes

      Les constantes sont utilis=E9es pour r=E9f=E9rencer = une valeur ou un=20 type sp=E9cifique.
      Elles permettent une meilleur lecture et = maintenance d'un=20 source.
      De tous types, elles sont utilis=E9es dans les entit=E9s, = architectures=20 ou packets.

      Syntaxe

      Exemple

        constant BUS_WIDTH : integer :=3D 8;







      D

      DELAY.

      Delay

      Voir AFTER.







      E

      ENTITY, EXIT.

      Entity

      D=E9clare une entit=E9 visible de l'ext=E9rieur.=20

      Syntaxe

      Exemple

        LIBRARY ieee;
        USE ieee.std_logic_1164.all;
        ENTITY fulladd = IS
          PORT (x,y,cin : IN bit;
          sum, cout : OUT bit);
        END = ulladd;

      Exit

      EXIT se combine avec FOR, WHILE et LOOP pour sortir = d'une boucle.=20

      Syntaxe

        EXIT [loop_label] [WHEN condition];







      F

      FOR, FUNCTION. =

      For

      FOR est une instruction de bouclage. Elle s'utilise = avec LOOP.
      On place la = condition=20 de fin de sortie dans l'instruction m=EAme contrairement au LOOP seul = o=F9 on est=20 oblig=E9 d'avoir recourt =E0 la commande EXIT. On peut toutefois = utiliser EXIT ou NEXT.
      Le bouclage = se fait=20 autant de fois que discrete_range l'indique.

      Syntaxe

        [loop_label:] FOR index_variable IN discrete_range LOOP
            sequence_of_statements
        END LOOP = [loop_label];

      Exemple

        USE ieee.std_logic_1164.all;
        ENTITY clock IS
          PORT (clk1 : INOUT std_logic :=3D '0');
        END = clock;
        ARCHITECTURE=20 behv OF clock IS
        CONSTANT pulse_time : time :=3D 25ns;
        BEGIN
          clkit: PROCESS
          VARIABLE a : integer :=3D 1;
          BEGIN
            loop1: FOR a IN 1 TO 10 LOOP -- la variable de boucle est a de 1 = =E0=20 10
              WAIT FOR pulse_time; -- attend la valeur de pulse_time
              clk1 = <=3D=20 NOT clk1; -- compl=E9mente clk1
            END LOOP = loop1;
          END PROCESS=20 clkit;
        END behv;

      Function

      Les FONCTIONS sont des blocs d'instructions qui = retournent une=20 valeur. Les fonctions peuvent =EAtre appel=E9es de diff=E9rents = endroits.
      Les=20 param=E8tres pass=E9s sont du type IN et les objets de class SIGNAL ou=20 CONSTANT.
      On peut d=E9clarer des variables locales =E0 l'int=E9rieur = d'une=20 fonction. Ces variables perdent leur valeur =E0 chaque sortie de la = fonction et=20 sont initialis=E9es =E0 chaque appel.
      Une fonction peut =EAtre = d=E9clar=E9e dans un=20 PACKAGE ou dans le corps d'une ARCHITECTURE.
      Une fonction autorise = qu'un=20 traitement s=E9quentiel (pas de PROCESS et WAIT) ni d'assignation d'un=20 signal.
      Une fonction doit comporter au moins une instruction = RETURN.
      Voir=20 aussi       PROCEDURE et PACKAGE.

      Syntaxe
      D=E9claration

        FUNCTION function_name
          {(parameter_list)}
          RETURN type_name;

      Corps = de la=20 fonction
        FUNCTION function_name
          {(parameter_list)}
          RETURN type_name IS
        BEGIN
          [block_statement]
          [generate_statement]
        END=20 [function_name];
      Exemple
        LIBRARY ieee;
        USE ieee.std_logic_1164.all;
        ENTITY nor2 IS
          GENERIC (tphl : time :=3D 10.0ns; -- d=E9claration des temps de=20 propagation
              tplh : time :=3D 15.0ns);
          PORT (a,b : IN = std_logic;
              z : OUT std_logic);
        END = nor2;

        ARCHITECTURE=20 behavior OF nor2 IS
        BEGIN
          dly: PROCESS(a,b)
          VARIABLE newstate : std_logic;
          BEGIN
            newstate :=3D a NOR b;
            z <=3D newstate AFTER delay(a NOR=20 b,tplh,tphl); -- appel de la fonction delay
          END PROCESS=20 dly;
        END behavior;

        LIBRARY ieee; -- d=E9claration de la fonction
        USE=20 ieee.std_logic_1164.all;
        USE work.myfuncs.all; -- on d=E9clare la=20 biblioth=E8que utilisateur myfuncs
        PACKAGE myfuncs IS
          FUNCTION delay(newval : IN std_logic; -- ent=EAte de delay
            delay01 : IN time; -- les param=E8tres n'ont pas le m=EAme nom, = c'est=20 l'ordre qui compte
          delay10 : IN time) RETURN time; -- = retourne un=20 nombre de type time
        END myfuncs;

        PACKAGE BODY myfuncs = IS
          FUNCTION delay(newval : IN std_logic; -- corps de delay
            delay01 : IN time;
          delay10 : IN time) RETURN=20 time;
        BEGIN
          CASE newval IS
            WHEN '0' =3D> RETURN delay01; -- retourne la valeur = delay01
            WHEN=20 '1' =3D> RETURN delay10; -- retourne la valeur delay10
            WHEN = OTHERS=20 =3D> IF (delay01 > delay10) THEN -- retourne la plus grande = valeur
              RETURN delay01;
            ELSE;
              RETURN delay10;
            END IF;
          END CASE;
        END=20 delay;
        END myfuncs;







      G

      GENERIC. =

      Generic

      La section GENERIC_DECLARATIONS dans l'ent=EAte ENTITY = permet de=20 d=E9finir des param=E8tres exploitables dans l'architecture.
      Cette = m=E9thode=20 d'=E9criture permet une maintenance plus ais=E9e.

      Syntaxe

      Exemple

        LIBRARY ieee;
        USE ieee.std_logic_1164.all;
        ENTITY nor2 IS
          GENERIC (tphlmin, tplhmin: time :=3D 3.0ns; -- d=E9claration des = temps de=20 propagation
            tphltyp : time :=3D 8.0ns;
            tplhtyp : time :=3D = 6.5ns;
            tphlmax,=20 tplhmax: time :=3D 13.0ns);
          PORT (a,b : IN std_logic;
            z : OUT std_logic);
        END nor2;

        ARCHITECTURE = behavior OF=20 nor2 IS
        BEGIN
          dly0: PROCESS(a,b);
          BEGIN
            IF a =3D '0' AND b =3D '0' THEN -- il faut r=E9soudre tous les = cas puisque=20 tplhtyp < > tphltyp
              z <=3D '1' AFTER tplhmin;
            ELSIF a =3D '0' AND b =3D = '1' THEN
              z <=3D '0' AFTER tphlmin;
            ELSIF a =3D '1' AND b =3D = '0' THEN
              z <=3D '0' AFTER tphlmin;
            ELSIF a =3D '1' AND b =3D = '1' THEN
              z <=3D '0' AFTER tphlmin;
            END IF;
          END = PROCESS=20 dly0;
        END behavior;







      H







      I

      IF...THEN, INERTIAL. =

      IF ... THEN

      La combinaison IF THEN permet d'effectuer un test = d'une=20 expression logique. La suite du d=E9roulement d=E9pend du = r=E9sultat.
      Deux=20 imbrications sont possibles : ELSIF suivi d'un autre test et ELSE qui = contr=F4le=20 les r=E9sultats FALSE.

      Syntaxe

        Exemple

          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY mux IS
            PORT (a,b,sel : IN std_logic;
                y : OUT std_logic);
          END mux;
          ARCHITECTURE = behavior OF=20 mux IS
          BEGIN
            PROCESS (sel,a,b) -- liste de sensibilit=E9
            BEGIN
              IF sel =3D '0' THEN -- test si sel vaut 0
                y <=3D a; -- si a=3D0 reproduit a sur y
              ELSIF sel = =3D '1' THEN --=20 test si sel vaut 1
                y <=3D b; -- si a=3D1 reproduit b sur y
              ELSE
                y <=3D 'X'; -- si sel n'est ni =E0 1 ni =E0 0, on affecte X = =E0=20 y
              END IF;
            END PROCESS;
          END=20 behavior;
        Exemple
          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY por IS
            PORT (int0,int1 : IN std_logic :=3D '1';
                p1_1,p1_2 : OUT std_logic :=3D '0'
                reset : INOUT std_logic = :=3D=20 '0');
          END por;
          ARCHITECTURE behv OF por = IS
          BEGIN
            pwrit: PROCESS
            VARIABLE init : boolean :=3D true; -- d=E9clare = une=20 variable init initialis=E9e =E0 TRUE
            BEGIN
              IF init =3D true THEN -- teste init
                WAIT FOR 150ns -- si init est TRUE, temporise 150ns
                reset = <=3D=20 '1'; -- positionne reset =E0 1
                init :=3D false; -- apr=E8s le = premier=20 passage, la variable init est pass=E9e =E0 FALSE
              ELSE -- = si init n'est=20 pas TRUE
                WAIT FOR 150ns; -- temporise 150ns
                reset <=3D '0'; -- = met reset=20 =E0 0. On suppose l'initialisation termin=E9e
              END = IF;
            END=20 PROCESS pwrit;

            ckint: PROCESS -- ce PROCESS est d=E9clanch=E9 = suivant la=20 liste d=E9finie par WAIT ON
            BEGIN
              IF reset =3D '1' THEN -- si reset est =E0 1
                IF int0 =3D '1' THEN -- si int0 est =E0 0
                  p1_1 <=3D '1'; -- place p1_1 =E0 1
                ELSIF int1 =3D = '1' THEN --=20 si int1 est =E0 1
                  p1_2 <=3D '1'; -- place p1_2 =E0 1
                END = IF;
              END=20 IF;
              WAIT ON int0, int1, reset; -- attend un changement d'=E9tat = d'un de=20 ces signaux
            END PROCESS ckint;
          END = behv;

        Inertial

        Voir AFTER.







        J







        K







        L

        LIBRARY, LOOP.

        Library

        D=E9clare une liste de biblioth=E8ques. Cette = instruction s'utilise=20 avec USE.
        Ll'instruction LIBRARY doit appara=EEtre au d=E9but du = fichier=20 source.
        Les biblioth=E8ques WORK et STD n'ont pas besoin d'=EAtre = d=E9clar=E9es.=20 Chaque d=E9veloppement incorpore implicitement les lignes suivantes : =

        Syntaxe

          LIBRARY library_name {, library_name};
          USE=20 library_name.package_name.declarative_unit;

        Exemple

          LIBRARY mylib;
          USE mylib.math.all;

        Loop

        LOOP est une instruction de bouclage. Elle peut = s'utiliser seule=20 ou avec FOR ou WHILE.
        Ici, elle = est=20 utilis=E9e seule pour r=E9p=E9ter une s=E9rie d'instructions. Dans ce = cas (lorsqu'elle=20 est utilis=E9e seule), la condition de fin de boucle est pr=E9cis=E9e = par=20 l'instruction EXIT ou NEXT por passer =E0 = l'it=E9ration=20 sauivante.

        Syntaxe

          [loop_label:] LOOP
              sequence_of_statements
          END LOOP = [loop_label];

        Exemple

          PROCESS (a) -- positionne z(a) =E0 1
            VARIABLE i : INTEGER RANGE 0 TO 4; -- d=E9clare une variable = enti=E8re=20 variant de 0 =E0 4
          BEGIN
            z <=3D "0000"; -- positione z =E0 0000
            i :=3D 0; -- = initialise i
            LOOP=20 -- marque le d=E9but de la boucle
              EXIT WHEN i =3D 4; -- condition pour sortir de la boucle
              IF = (a =3D i)=20 THEN -- teste si a =3D i
                z(i) <=3D '1'; -- met z indice i =E0 1
              END IF;
              i = :=3D i + 1;=20 -- incr=E9mente i
            END LOOP; -- fin de la = boucle
          END=20 PROCESS;






        M

        MOD.

        Mod

        Voir les op=E9rateurs.







        N

        NAND, NEXT, NOR, NOT, NULL.

        Nand

        Voir les op=E9rateurs.

        Next

        NEXT se combine avec FOR, WHILE et LOOP pour passer =E0 = l'it=E9ration=20 suivante.

        Syntaxe

          NEXT [loop_label] [WHEN condition];

        Nor

        Voir les op=E9rateurs.

        Not

        Voir les op=E9rateurs.

        Null

        Null est l'instruction qui n'effectue pas d'action.=20

        Syntaxe







        O

        OPERATEURS, OR.

        Op=E9rateurs

        Le tableau suivant r=E9sume les op=E9rateurs VHDL.

        = =
        Classe Symbole Fonction Definit pour
        Op=E9rateurs=20 divers

        Classe de plus haute priorit=E9        		 not
        **
        abs        		 compl=E9ment
        exponentiel
        valeur absolue        		 bit, bool=E9en
        entier, r=E9el
        num=E9rique

        Op=E9rateurs=20 multiplicatifs        		 *
        /
        mod
        rem        		 multiplication
        division
        modulo
        reste
        num=E9rique

        entier
        Signe
        (unaire)=         		+
        -        		 positif
        n=E9gatif
        num=E9rique

        Op=E9rateurs=20 additifs
        (binaire)        		 +
        -
        &        		 addition
        soustraction
        concat=E9nation
        num=E9rique
        1 dimension

        Op=E9rateurs=20 relationnels        		 =3D
        /=3D
        <
        >
        <=3D
        >=3D        		=E9gal
        diff=E9rent
        inf=E9rieur
        sup=E9rieur
        inf=E9rieur = ou=20 =E9gal
        sup=E9rieur ou =E9gal        		 tous les types
        retournent un = bool=E9en

        Scalaire
        retourne un=20 bool=E9en

        Op=E9rateurs=20 logiques
        (binaire)

        Classe de plus faible = priorit=E9        		 and
        or
        nand
        nor
        xor        		 et logique
        ou logique
        et non logique
        ou non = logique
        ou=20 exclusif
        bit
        bool=E9en
        vecteur

        Les op=E9rateurs sont d=E9finis pour des classes particuli=E8res.

        La classe des = op=E9rateurs=20 Divers

        Ces op=E9rateurs permettent la compl=E9mentarit=E9, la = fonction=20 exponentielle et la recherche de la valeur absolue d'un nombre.
        Ils=20 retournent une valeur de m=EAme type.

        La classe des op=E9rateurs = Logiques

        Les op=E9rateurs logiques doivent =E9ffectuer une op=E9ration = sur les types=20 bit, bool=E9en, bit_vector, tableau lin=E9aire de bool=E9ens, std_logic = et=20 std_logic_vector. Ils retournent une valeur de m=EAme type.

        Exemple

        La = classe des=20 op=E9rateurs Relationels

        Les op=E9rateurs =E9galit=E9 et in=E9galit=E9 sont d=E9finis = pour tous les types.=20 Ils retournent un bool=E9en.

        Les autres op=E9rateurs relationels sont d=E9finis pour tous les = types scalaires=20 et pour toutes les dimensions. Ils retournent =E9galement un bool=E9en.

        Exemple

          '0' =3D '0'; -- =E9valu=E9 =E0 TRUE
          "101" < "110"; -- = =E9valu=E9 =E0=20 TRUE

          constant ARR1 :bit_vector :=3D "0011";
          constant ARR2 = :bit_vector=20 :=3D "01";
          -- (ARR1 < ARR2) will return true car la comparaison = s'effectue=20 bit =E0 bit de gauche =E0 droite.
        La classe des op=E9rateurs Additifs

        Les additions et soustractions sont permises pour les = op=E9randes=20 num=E9riques. Les op=E9randes doivent =EAtre de m=EAme type.
        La = concat=E9nation est=20 autoris=E9e pour les tableaux =E0 une dimension.

        Exemple

          CONSTANT s1 : string(1 TO 4):=3D"ABCD";
          CONSTANT s2 : string(1 TO = 4):=3D"EFGH";
          CONSTANT s3 : string(1 TO 8):=3Ds1 & s2; --=20 "ABCDEFGH"
        Exemple
          ENTITY concat IS
            PORT (a,b,c : IN std_logic;
                d : OUT std_logic_vector( 2 DOWNTO 0));
          END=20 concat;
          ARCHITECTURE behav OF concat IS
          BEGIN
            d <=3D NOT(a) & NOT(b) & NOT(c); -- d est un vecteur = form=E9 des=20 compl=E9ments de a, b et c
          END behav;
        La classe Signe

        Cette petite classe permet de sp=E9cifier le signe d'un = op=E9rateur.

        Exemple

          a/-b; -- ill=E9gal
          a/(-b); -- l=E9gal
        La classe des op=E9rateurs Multiplicatifs

        Cette classe permet des op=E9randes de types diff=E9rents. Les = exemples=20 suivants illustrent cette particularit=E9.

        Exemple

          9 ns * 8 =3D 72ns; -- le r=E9sultat est du type physique
          9 ns / 3 = =3D 3; --=20 le r=E9sultat est du type num=E9rique
          9 ns * 8 ns -> = l'op=E9ration provoque=20 une erreur de compilation

        Or

        Voir les op=E9rateurs.







        P

        PACKAGE, PORT, PORT MAP, PROCEDURE, PROCESS. =

        Package

        PACKAGE d=E9clare une fonction ou une = proc=E9dure.
        Le nom d=E9fini=20 par PACKAGE BODY doit =EAtre le m=EAme que celui d=E9clar=E9 par = PACKAGE.
        Voir aussi=20         FUNCTION et = PROCEDURE.

        Syntaxe
        D=E9claration

          PACKAGE package_name IS
          =
            [type_declaration]
            [subtype_declaration]
            [constant_declaration]=
            .
            .
            [component_declaration]
          END=20 [package_name];

        Corps du PACKAGE

          PACKAGE BODY package_name IS
          =
            [type_declaration]
            [subtype_declaration]
            [constant_declaration]=
            .
            .
            [subprogram_declaration]
          END=20 [package_name];

        Exemple

          PACKAGE math IS -- d=E9claration de l'ent=EAte du = package
          FUNCTION minval=20 (CONSTANT a,b : IN integer)
          RETURN integer;
          FUNCTION maxval = (CONSTANT=20 a,b : IN integer)
          RETURN integer;
          CONSTANT maxint:=20 integer:=3D16#FFFF#;
          END math;

          PACKAGE BODY math IS -- d=E9inition du corp du package
          FUNCTION = minval=20 (CONSTANT a,b : IN integer) RETURN integer IS
          BEGIN

            IF a < b THEN
              RETURN a;
            ELSE
              RETURN b;
            END IF;
          END minval;
          FUNCTION maxval = (CONSTANT=20 a,b : IN integer) RETURN integer IS
          BEGIN
            IF a > b THEN
              RETURN a;
            ELSE
              RETURN b;
            END IF;
          END = maxval;


        Port

        PORT d=E9crit un signal externe et visible d'une = entit=E9. Tous les=20 PORT ont un mode ainsi qu'un type. Les PORT permettent la communication = de=20 l'architecture.
        Le mode par d=E9faut est IN.=20

        Syntaxe

        Exemple

          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY fulladd = IS
            PORT (x,y,cin : IN bit;
            sum, cout : OUT bit);
          END=20 fulladd;


        Port Map

        PORT MAP est utilis=E9 pour associer les broches d'un = COMPONENT avec = les=20 signaux du montage.
        Deux m=E9thodes d'affectation sont possibles = :

        • par l'association des noms ;
        • par l'association des positions (la plus courante).

        Syntaxe

          PORT MAP (pin_name =3D> signal_name
              {, pin_name =3D> signal_name});

          PORT MAP = (signal_name {,=20 signal_name});


        Procedure

        Les PROCEDURES sont des blocs d'instructions qui = permettent=20 d'=E9ffectuer des calculs et qui peuvent =EAtre appel=E9es de = diff=E9rents=20 endroits.
        Les param=E8tres pass=E9s sont du type IN, OUT et INOUT et = les objets=20 de classe SIGNAL, CONSTANT ou VARIABLE. Le mode par d=E9faut du type IN = est de=20 classe CONSTANT. OUT et INOUT sont consid=E9r=E9s comme de classe = VARIABLE. En fait,=20 le param=E8tre CONSTANT IN peut =EAtre associ=E9 avec un signal, = variable, constante=20 ou une expression lorsque la proc=E9dure est appel=E9e.
        Une = proc=E9dure peut =EAtre=20 d=E9clar=E9e dans un PACKAGE ou dans le corps d'une ARCHITECTURE.
        On = peut=20 d=E9clarer des variables locales =E0 l'int=E9rieur d'une proc=E9dure. = Ces variables=20 perdent leur valeur =E0 chaque sortie de la proc=E9dure et sont = initialis=E9es =E0=20 chaque appel.
        Bien qu'une PROCEDURE ne retourne pas de valeur = contrairement =E0=20 une FONCTION, on peut d=E9clarer dans son ent=EAte plusieurs = param=E8tres de type OUT=20 ou INOUT et ainsi r=E9cup=E9r=E9s des valeurs de sortie.
        Une = proc=E9dure peut=20 contenir un WAIT sauf si elle est appel=E9e par un PROCESS avec une = liste de=20 sensibilit=E9 ou depuis une FONCTION.
        Voir aussi FUNCTION         et PACKAGE.

        Syntaxe
        D=E9claration

          PROCEDURE procedure_name
            {(parameter_list)};

        Corps de la = proc=E9dure
          PROCEDURE procedure_name
            {(parameter_list)}
          BEGIN
            [block_statement]
            [generate_statement]
          END=20 [procedure_name];
        Exemple
          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          USE = work.myfuncs.all; --=20 on d=E9clare la biblioth=E8que utilisateur myfuncs
          ENTITY = parity_add IS
            PORT (din : std_logic_vector(7 DOWNTO 0);
                douto, doute : OUT std_logic_vector(8 DOWNTO = 0));
          END=20 parity_add;

          ARCHITECTURE behv OF parity_add IS
          BEGIN
            PROCESS(din)
            VARIABLE dintemp : std_logic_vector(7 DOWNTO=20 0);
            VARIABLE dptempo,dptempe : std_logic_vector(8 DOWNTO = 0);
            BEGIN
              dintemp :=3D = din;
              addparity(dintemp,dptempo,dptempe);
              douto <=3D=20 dptempo;
              doute <=3D dptempe;
            END = PROCESS;
          END behv;

          LIBRARY ieee; -- d=E9claration de la proc=E9dure
          USE=20 ieee.std_logic_1164.all;
          PACKAGE myfuncs IS
            PROCEDURE addparity(VARIABLE d : IN std_logic_vector(7 DOWNTO = 0);
              do, de : OUT std_logic_vector(8 DOWNTO 0)); -- les param=E8tres = n'ont=20 pas le m=EAme nom, c'est l'ordre qui compte
          END=20 myfuncs;

          PACKAGE BODY myfuncs IS
            PROCEDURE addparity(VARIABLE d IN std_logic_vector(7 DOWNTO 0); -- = corps=20 de la proc=E9dure
              do, de : OUT std_logic_vector(8 DOWNTO 0)) IS -- do et de sont = les=20 valeurs de sorties de la proc=E9dure
              VARIABLE temp :=20 std_logic;
              BEGIN
                temp :=3D '0';
                loop1: FOR i IN 7 DONWTO 0 LOOP
                  temp :=3D temp XOR d(i);
                END LOOP loop1;
                de :=3D = temp &=20 d;
                do :=3D NOT temps & d;
            END = addparity;
          END=20 myfuncs;

        Process

        Un PROCESS est une d=E9claration concurrente dans une=20 architecture. Un PROCESS peut =EAtre sensible =E0 une liste de signaux = ou =E0 un=20 WAIT.
        Les PROCESS contiennent seulement des d=E9clarations = s=E9quentielles qui=20 sont ex=E9cut=E9es dans l'ordre sp=E9cifi=E9.

        Syntaxe

          [label]: PROCESS [(sensitive_signal_name {, = sensitive_signal_name})]
          =
            [constant_declarations]
            [variable_declarations]
          BEGIN
            [sequential_statements]
          END PROCESS [label];

        Exemple

          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY nor2 IS
            PORT (a,b : IN std_logic:=3D'0';
              qn : OUT std_logic);
          END nor2;

          ARCHITECTURE = proc_behv=20 OF nor2 IS
          BEGIN=20
            ex1: PROCESS(a,b) -- ce PROCESS est d=E9crit avec une liste de=20 sensibilit=E9
            BEGIN=20
              qn <=3D a NOR b;
            END PROCESS ex1;

            ex2: PROCESS = -- ce=20 PROCESS n'a pas de liste de sensibilit=E9
            BEGIN=20
              qn <=3D a NOR b;
              WAIT ON a,b; -- WAIT permet d'attendre un = =E9v=E9nement sur a ou b
            END PROCESS ex2;
          END = proc_behv;=20

        Exemple
          SENSE_PROC: PROCESS (CLK)
          begin
            if CLK'event and CLK=3D'1' then
              Q2 <=3D D2;
            END IF;
          END PROCESS=20 SENSE_PROC;

          WAIT_PROC: PROCESS
          begin
            WAIT UNTIL CLK'event and CLK=3D'1';
            Q1 <=3D D1;
          END = PROCESS=20 WAIT_PROC;







        Q







        R

        REM, RETURN. =

        Rem

        Voir les op=E9rateurs.

        Return

        Voir FUNCTION.







        S

        SELECT, SIGNAL, SUBTYPE. =

        Select

        Dans la fonctionnalit=E9, SELECT est =E9quivalent =E0 = l'instruction CASE. SELECT ne peut = toutefois=20 affecter qu'une seule variable.

        Syntaxe

          [label:] WITH expression SELECT
                target <=3D waveform1 WHEN choices 1
                        {waveform1 WHEN choices N},
                        waveform1 WHEN=20 OTHERS;

        Exemple

          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY mux IS
            PORT (a,b,sel : IN std_logic;
                y : OUT std_logic);
          END mux;
          ARCHITECTURE = behavior OF=20 mux IS
          BEGIN
            muxex: WITH sel SELECT
              y <=3D a WHEN '0',-- y =3D a si sel =3D 0 sinon
                    b WHEN '1', -- y =3D b si sel =3D 1 sinon
                    'X' WHEN = OTHERS; -- y=20 est ind=E9termin=E9
          END = behavior;
        Signal

        SIGNAL d=E9clare un signal permettant la communication = entre les=20 =E9tats concurrents =E0 l'int=E9rieur d'une architecture.
        Dans la = d=E9finition, on=20 doit sp=E9cifier un type au signal et l'on peut attribuer une valeur par = d=E9faut.

        Syntaxe

          SIGNAL sig_name {, sig_name} : signal_type=20 [:=3Dinitial_value];
        On assigne une valeur =E0 un signal en = suivant ce=20 format :
          sig_name <=3D expression;

        Exemple

          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY fulladd = IS
            PORT (x,y,cin : IN bit;
              sum, cout : OUT bit);
          END = fulladd;

          ARCHITECTURE=20 behavior OF fulladd IS
            SIGNAL sum1, cout1, cout2, cout3 : bit;
          BEGIN
            sum <=3D sum1 XOR cin;
            sum1 <=3D x XOR y;
            cout1 = <=3D x AND=20 y;
            cout2 <=3D x AND cin;
            cout3 <=3D y AND cin;
            cout = <=3D cout1=20 OR cout2 or cout3;
          END behavior;

        Exemple

          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY compar2 = IS
            PORT (a1, b1, a2 : IN bit :=3D '0';
              c1 : INOUT bit;
              c2 : OUT bit);
          END=20 compar2;

          ARCHITECTURE behavior OF compar2 IS
          BEGIN
            c1 <=3D a1 XOR b1;
            c2 <=3D c1 XOR a2;
          END=20 behavior;

        Subtype

        SUBTYPE d=E9clare un type qui est la combinaison de = deux autres=20 types.
        Voir aussi         TYPE.

        Exemple

          TYPE colors IS (red, yellow, blue, green, black);
          SUBTYPE primary = IS=20 colors RANGE red TO blue;

          TYPE integer IS RANGE -2147483647 TO=20 2147483647;
          SUBTYPE absolu IS integer 0 TO 2147483647;

          TYPE = area IS=20 ARRAY (natural RANGE <>, natural RANGE <>)
            OF bit;
          SUBTYPE small_area IS area (0 TO 10, 0 TO=20 10);







        T

        TRANSPORT, TYPE.

        Transport

        Voir AFTER.

        Type

        Les TYPES pr=E9d=E9finis

        Les types pr=E9d=E9finis reconnaissent six objets scalaires = :

        Dans la=20 biblioth=E8que IEEE STD_LOGIC_1164 TYPE les types usuels sont d=E9j=E0 = d=E9clar=E9s.
        Le=20 type std_ulogic contient 9 =E9l=E9ments de base.

          'U' - Unitialized (=E9l=E9ment de plus haute priorit=E9)
          'X' - = Forcing=20 Unknown
          '0' - Forcing 0
          '1' - Forcing 1
          'Z' - High = impedance
          'W' -=20 Weak unknown
          'L' - Weak 0
          'H' - Weak 1
          '-' - Don't care = (=E9l=E9ment de=20 plus basse priorit=E9)

        Ces objets scalaires peuvent =EAtre plac=E9s dans un = contexte=20 diff=E9rent suivant leur d=E9claration.

        Le = TYPE =E9num=E9r=E9

        TYPE permet de d=E9finir un type utilisateur auquel on peut = assigner un=20 objet.
        Tous les objets doivent =EAtre assign=E9s =E0 un type. Chaque = TYPE d=E9clar=E9=20 doit =EAtre unique.

        Syntaxe

          TYPE identifier IS enumeration_type_literals;

        Exemple

          TYPE op_type IS (opadd, opor, opand, opxor);
          TYPE letters IS = ('A', 'a',=20 'R', 'r');
          TYPE std_ulogic IS ('U', 'X', '0', '1', 'Z', 'W', 'L', = 'H',=20 '-');=20

        Le TYPE num=E9rique

        Cette d=E9finition de type doit =EAtre dans une =E9chelle de = valeur.
        La=20 base par d=E9faut est la d=E9cimale.

        Syntaxe

          TYPE identifier IS RANGE implementation_defined;

        Exemple

          TYPE byte IS RANGE 0 to 255; -- byte varie de 0 =E0 255
          TYPE = index IS=20 RANGE 7 DOWNTO 0; -- index varie de 7 =E0 0
          SUBTYPE byte IS INTEGER = RANGE 0=20 TO 255; -- byte est un entier de 0 =E0 255=20

        Le TYPE physique

        Cette d=E9finition de type repr=E9sente une quantit=E9 = physique.
        La base=20 des unit=E9s doit =EAtre sp=E9cifi=E9e. Les valeurs sont calcul=E9es =E0 = partir de cette=20 base.

        Syntaxe

          TYPE identifier IS RANGE implementation_defined;
            UNITS
            =
              base_unit_declaration
              [secondary_unit_declaration]
            END = UNITS;=20

        Exemple

          TYPE time IS RANGE implementation_defined;
            UNITS=20
              fs;
              ps =3D 1000fs;
              ns =3D 1000fs;
              us =3D 1000ns;
              ms = =3D=20 1000us;
              sec =3D 1000ms;
              min =3D 1000sec;
              hr =3D = 1000min;
            END=20 UNITS;

        Le TYPE tableau

        Le type tableau est un groupement de types identiques.
        Les = tableaux=20 peuvent =EAtre multidimentionels.
        Il existe deux sortes de tableaux = :
        Les=20 tableaux avec contrainte (Constrained Array)

          Ces tableaux sont d=E9finis avec des dimensions fig=E9es (rang=E9es=20 colonnes).
        Les tableaux sans contrainte (Unconstrained = Array)
          Ces tableaux sont d=E9finis sans pr=E9ciser les dimensions. Le = tableau est=20 donc dynamique.

        Syntaxe

          TYPE identifier IS ARRAY
          =
            [unconstrained_array_definition];
            [constrained_array_definition];<= BR>

        Exemple

          TYPE data_bus IS ARRAY (0 TO 31) OF bit; -- tableau de 32 = bit
          TYPE bit4=20 IS ARRAY (3 DOWNTO 0) OF bit; -- tableau de 4 bit : bit4(3) =E0=20 bit4(0)

          TYPE string IS ARRAY (positive RANGE <>) OF=20 character;
          TYPE bit_vector IS ARRAY (natural RANGE <>) OF=20 bit;

          TYPE dim2 IS ARRAY (0 TO 7, 0 TO 7) OF bit; -- tableau =E0 = deux=20 dimensions







        U

        USE.

        Use

        Voir LIBRARY.







        V

        VARIABLE. =

        Variable

        Les variables sont utilis=E9es dans un PROCESS, une = PROCEDURE ou=20 une FONCTION.
        On peut leur donner une valeur initiale. Cette valeur = initiale=20 est attribu=E9e =E0 chaque appel de la PROCEDURE ou de la FONCTION. = Elles servent =E0=20 manipuler des variables temporaires/interm=E9diaires pour faciliter le=20 d=E9veloppement d'un algorithme s=E9quentiel.

        Syntaxe

        Exemple

          VARIABLE i : INTEGER RANGE 0 TO 3; -- valeur intiale 0
          VARIABLE x = :=20 std_ulogic; -- valeur intiale 'U'
        Exemple
          FUNCTION parity (x : std_ulogic_vector) -- recherche la parit=E9 = d'un=20 vecteur
                RETURN std_ulogic IS
            variable tmp : std_ulogic = :=3D=20 '0';
          begin
            FOR j IN x'RANGE LOOP
              tmp :=3D tmp XOR x(j);
            END loop; -- fin de la = boucle
            RETURN=20 tmp;
          END parity;







        W

        WAIT, WHEN, WHILE, WITH, WORK.

        Wait

        WAIT est utilis=E9 dans une d=E9claration = s=E9quentielle de type=20 PROCESS ou PROCEDURE.
        WAIT remplace une liste de sensibilit=E9 pour = contr=F4ler=20 l'ex=E9cution et la suspension d'un PROCESS.
        WAIT peut =EAtre plac=E9 = n'importe o=F9=20 dans le PROCESS.
        Sans WAIT ou sans liste de sensibilit=E9, un PROCESS = se boucle=20 ind=E9finiment.

        Il existe trois syntaxes diff=E9rentes autour de = WAIT.

        WAIT ON est =E9quivalent =E0 une liste de sensibilit=E9. La liste des = signaux=20 suit.
        Ainsi :


        est = =E9quivalent =E0=20 :
          process
          begin
            -- sequential statements
            WAIT ON a,b;
          end=20 process;

        La condition test=E9e par WAIT UNTIL d'expression = bool=E9enne=20 doit parvenir =E0 TRUE pour continuer l'ex=E9cution.
          process
          begin
            wait until CLK'event and CLK=3D'1';
            Q1 <=3D D1;
          end=20 process;
        Le temps imparti par WAIT FOR sp=E9cifie la = dur=E9e maximale=20 pendant laquelle le PROCESS reste suspendu.
          STIMULUS: process
          begin
              EN_1 <=3D '0';
              EN_2 <=3D '1';
            wait for 10 ns; = -- attend=20 10ns avant de passer =E0 la ligne suivante
              EN_1 <=3D '1';
              EN_2 <=3D '0';
            wait for 10 = ns;
              EN_1 <=3D '0';
            wait; -- attent = ind=E9finiment
          end process=20 STIMULUS;
        Exemple
          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY upcont = IS
            PORT (i : INOUT integer:=3D1; -- d=E9clare et initialise i =E0 = 1
            clk : IN=20 std_logic:=3D'0';
            count : OUT integer);
          END=20 upcont;

          ARCHITECTURE cpt OF upcont IS
          BEGIN
            sens1: PROCESS
            BEGIN
              i <=3D i+1; -- incr=E9mente i. i vaut 2 apr=E8s le premier=20 passage
              WAIT ON clk; -- attend une transition de clk (front = montant ou=20 descendant)
            END PROCESS sens1;

            sens2: = PROCESS
            BEGIN
              count <=3D i; -- met =E0 jour la sortie count
              WAIT ON i; = -- attend=20 un changement de i
            END PROCESS sens2;
          END cpt;

        When

        WHEN est utilis=E9 dans une liste de s=E9lection avec = l'instruction=20 CASE.
        On le = retrouve=20 aussi lors de l'assignement conditionnel d'un signal. Dans cette = utilisation, il=20 remplace l'=E9criture du IF THEN avantageusement car il permet = l'imbrication des=20 tests.

        Syntaxe

          [label:] target <=3D [options] value_expression [AFTER = time_expression]=20 WHEN condition1
                ELSE
                  [options] value_expression [AFTER time_expression] WHEN=20 condition2;

        Exemple

          LIBRARY ieee;
          USE ieee.std_logic_1164.all;
          ENTITY mux IS
            PORT (a,b,sel : IN std_logic;
                y : OUT std_logic);
          END mux;
          ARCHITECTURE = behavior OF=20 mux IS
          BEGIN
            muxex: y <=3D a WHEN sel =3D '0' ELSE -- y =3D a sir sel =3D 0 = sinon
                  b WHEN sel =3D '1' ELSE -- y =3D b si sel =3D 1 = sinon
                  'X'; -- y est=20 ind=E9termin=E9
          END behavior;

        While

        WHILE est une instruction de bouclage. Elle s'utilise = avec LOOP.
        On place la = condition=20 de fin de sortie dans l'instruction m=EAme contrairement au LOOP seul = o=F9 on est=20 oblig=E9 d'avoir recourt =E0 la commande EXIT. On peut toutefois = utiliser EXIT ou NEXT.
        Le bouclage = se fait=20 tant que la condition reste TRUE.
        Remarque : si la condition est = FALSE d=E8s le=20 d=E9part, la boucle ne sera pas ex=E9cut=E9e une seule fois.

        Syntaxe

          [loop_label:] WHILE condition LOOP
              sequence_of_statements
          END LOOP = [loop_label];

        Exemple

          USE ieee.std_logic_1164.all;
          ENTITY clock IS
            PORT (clk1 : INOUT std_logic :=3D '0');
          END = clock;
          ARCHITECTURE=20 behv OF clock IS
          CONSTANT pulse_time : time :=3D 25ns;
          BEGIN
            clkit: PROCESS
            VARIABLE a : integer :=3D 1;
            BEGIN
              loop1: WHILE (a <=3D 10) LOOP -- la variable de boucle est a=20 inf=E9rieure =E0 10
                WAIT FOR pulse_time; -- attend la valeur de pulse_time
                clk1 = <=3D=20 NOT clk1; -- compl=E9mente clk1
                a :=3D a + 1; -- = incr=E9mentation de=20 a
              END LOOP loop1;
            END PROCESS clkit;
          END = behv;

        With

        Voir SELECT.

        Work

        Voir Library.







        X

        XOR.

        Xor

        Voir les op=E9rateurs.







        Y







        Z






        ?

        +, -, *, **, /, &, =3D, >, <, <=3D, = >=3D

        Voir les op=E9rateurs.

        Index

        ABS, AFTER, AND, ARCHITECTURE,= ASSERT, ATTRIBUTS.
        CASE, CASSE, COMMENTAIRE, = COMPONENT, CONFIGURATION, CONSTANT.
        DELAY.
        ENTITY, EXIT.
        FOR, FUNCTION.
        GENERIC.
        IF...THEN, INERTIAL.
        LIBRARY, LOOP.
        MOD.
        NAND, NEXT, NOR, NOT, NULL.
        OPERATEURS, OR.
        PACKAGE, PORT, PORT MAP, PROCEDURE, PROCESS.
        REM, RETURN.
        SELECT, SIGNAL, SUBTYPE.
        TRANSPORT, TYPE.
        USE.
        VARIABLE.
        WAIT, WHEN, WHILE, WITH, WORK.
        XOR.
        =






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